The present invention relates to a semiconductor device having a feedback loop for internal signal synchronization to an external signal. More specifically, the invention relates to a delay setting in the feedback loop. The invention relates to the delay time setting in the feedback loop in a clock synchronization circuit typified by a DLL (delay-locked loop) circuit, for example, and further relates to a technique that is effective for being applied to clock reproduction for reproducing the phase of an input clock signal for use as the phase of an output clock signal.
Clock synchronization memories such as a synchronous DRAM have a DLL circuit. In the DLL circuit, an external clock signal is delayed by predetermined cycles, thereby reproducing the phase of an input clock signal for use as the phase of an output clock signal. Then, using the clock reproduction, an output timing of read data is synchronized with the phase of the output clock signal. The DLL circuit has the feedback loop for clock phase control. When the phase of the input clock signal is reproduced for use as the phase of the output clock signal, a delay circuit simulating a delay generated in an on-chip circuit configuration and a chip package should be provided for the feed back loop, and then feedback control of a phase difference between a feedback clock signal and a reference clock signal in the feedback loop should be exercised. In order to reproduce the phase of the input clock signal for use for the output clock signal, it becomes necessary to consider compatibility between the synchronization circuit and delay components caused by inductance components such as those of bonding pads, wires, bump electrodes, and leads and electrostatic capacitance components as well. In the circuit that simulates these delay components, an error from an actual delay might be generated due to the influence of variations in the semiconductor processing technology and changes in the temperature of the devices of the circuit. JP-A-2000-231421 discloses a technique for providing an off-chip driver, a clock receiver, and wiring in the feedback loop to simulate a system clock delay.